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Renesas Electronics /R7FA6M3AH /GLCDC /OUT_CLKPHASE

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Interpret as OUT_CLKPHASE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)TCON3EDGE 0 (0)TCON2EDGE 0 (0)TCON1EDGE 0 (0)TCON0EDGE 0 (0)LCDEDGE 0 (0)FRONTGAM

FRONTGAM=0, TCON1EDGE=0, TCON2EDGE=0, TCON3EDGE=0, LCDEDGE=0, TCON0EDGE=0

Description

Output Control Block Output Phase Control Register

Fields

TCON3EDGE

LCD_TCON3 Output Phase Control

0 (0): In synchronization with the rising edge of LCD_CLK.

1 (1): In synchronization with the falling edge of LCD_CLK.
TCON2EDGE

LCD_TCON2 Output Phase Control

0 (0): In synchronization with the rising edge of LCD_CLK.

1 (1): In synchronization with the falling edge of LCD_CLK.
TCON1EDGE

LCD_TCON1 Output Phase Control

0 (0): In synchronization with the rising edge of LCD_CLK.

1 (1): In synchronization with the falling edge of LCD_CLK.
TCON0EDGE

LCD_TCON0 Output Phase Control

0 (0): In synchronization with the rising edge of LCD_CLK.

1 (1): In synchronization with the falling edge of LCD_CLK.
LCDEDGE

LCD_DATA Output Phase Control

0 (0): In synchronization with the rising edge of LCD_CLK.

1 (1): In synchronization with the falling edge of LCD_CLK
FRONTGAM

Correction control

0 (0): Brightness/contrast correction is followed by gamma correction.

1 (1): Gamma correction is followed by brightness/contrast correction.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data